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                      | HITACHI HOME | UP | SEARCH | HITACHI

                      News Release

                      February 13, 1997

                      Hitachi Releases 4-Mbit Synchronous Fast SRAM Products for SPARC(TM) Processor Secondary Cache Memories

                      - High-speed 7.0ns clock access in input register/output latch mode -

                      Hitachi, Ltd., has developed two 4-Mbit synchronous fast SRAMs for secondary cache(*1) systems of servers and engineering workstations that use a SPARC(TM)(*2) processor. The HM67S36130BP has a 128k-word-by-36-bit (including parity) organization and HM67S18258BP has a 256k-word by 18-bit (including parity) organization. Sample shipments will begin in March 1997 in Japan. These products achieve a 7.0ns clock access in input register/output latch mode and support high-density mounting by adopting BGA (ball grid array) packaging(*3).

                      Synchronous fast SRAMs, can take full advantage of the performance of microprocessors, used the secondary cache memory in high-end workstations. The new SRAMs are a response to the market needs of higher speed and higher density. These SRAMs achieve the industry's fastest level 7.0ns clock access in the input register/output latch mode. The use of the input register/output latch mode are that a dummy cycle, which is in a pipelined transfer, is not required. To support high-frequency writes, the SRAMs support a late write function in which write data is applied one cycle later than the write address. To implement this function, the SRAM incorporates write buffers and bypass comparators. A byte write enable function is also provided so that write control is also possible in byte units.

                      LVCMOS levels were adopted as the address and control signal input and output levels for easy interfacing with SPARC(TM) processors, while a PECL differential input narrow amplitude interface was adopted for the main clock input for optimal support of high operating speeds. Furthermore, those SRAMs support a power down mode function to respond to the need for reduced power and provides a power down mode control pin.

                      These products are provided in a plastic BGA package in a Hitachi memory product. This package is a 119-pin 14-by-22 mm package with a wide 1.27-mm ball pitch, and thus allows high-density mounting while providing superlative heat dissipation characteristics and easy mounting. Additionally, since these products allow mutual connectivity checking during module mounting at the board level, it supports limited IEEE(*4) standard test access ports and boundary scan architecture (IEEE standard 1149.1-1990).

                      These products are fabricated in a 0.4 micrometer Bi-CMOS process. The HM67S36130BP uses a 128-kword-by-36-bit (including parity) organization and the HM67S18258BP a 256-kword-by-18-bit (including parity) organization.

                      Notes:
                      *1 Cache memory
                      A high-speed read/write memory system between the CPU and main memory. Cache memory holds copies of the sections of main memory most commonly referenced by the CPU to make up for the difference between CPU and main memory speeds. This increases the speed at which the CPU can execute instructions.
                      *2 SPARC(TM) is a trademark of Sun Microsystems.
                      *3 BGA (ball grid array) package
                      A surface mounting package that uses solder balls arranged in a grid array instead of the lead pins normally used in QFP, PGA, and other packages. The BGA package is easier to mount than many other packages, since the lead pitch is wider than, for example, a QFP package with the same number of pins.
                      *4 IEEE
                      Institute of Electrical and Electronics Engineers, Inc.

                      Features:
                      1. Realization of 7.0ns clock access in input register/output latch mode
                      These two SRAMs achieve the industry's fastest clock access of 7.0ns in input register/output latch mode.
                      2. Dummy cycle is not required.
                      As these products adopt the input register/output latch mode, a dummy cycle is not required. Thus these products contribute to higher performance system design.
                      3. 128-kword-by-36-bit organization and 256-kword-by-18-bit organization
                      These organizations support the easy implementation of optimal cache memory systems for engineering workstation and server applications that require parity bits.
                      4. Other features
                      (1) Later write function
                      (2) Byte write function
                      (3) Plastic 119-pin BGA package that allows high-density mounting
                      (4) Boundary scan function

                      Application Product Examples
                      - Engineering workstations and servers based on the SPARC(TM) processor

                      Pricing in Japan
                      Product Word organization Sample price
                      HM67S36130BP-7 128kword x 36bit 26,000 yen
                      HM67S18258BP-7 256kword x 18bit 26,000 yen

                      Specifications
                      Item HM67S36130BP HM67S18258BP
                      Word organization 128 kword by 36 bits 256 kword by 18 bits
                      Power-supply voltage 3.3 V +/- 5%
                      Operating temperature Ta = 0 to 70 degrees centigrade
                      Data transfer technique Non-pipelined transfer
                      Protocols Single clock (differential)/input register, output latch mode
                      Cycle time
                      (Operating frequency)
                      8.0 ns (max.)
                      (125MHz)
                      Clock access time 7.0 ns (max.)
                      Process 0.4 micrometer Bi-CMOS
                      Package Plastic 119-pin BGA
                      Main functions Power down mode
                      Late write/byte write
                      Boundary scan

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                      WRITTEN BY Secretary's Office
                      All Rights Reserved, Copyright (C) 1997, Hitachi, Ltd.

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