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                      | HITACHI HOME | UP | SEARCH | HITACHI

                      News Release

                      November 25, 1997

                      Hitachi Releases SH7612 SH-DSP with On-Chip Cache Memory For Multimedia Equipment

                      - Real-Time processor with 4-kbyte cache and large-capacity 16-kbyte RAM on-chip -

                      Hitachi, Ltd. today announced the release of a new series of SH-DSPs, combining RISC and DSP features, designated the SH7610 series, which include on-chip cache memory and are mainly intended for use in multimedia equipment such as Internet TVs and digital still cameras. As the initial product in this series, Hitachi is releasing the SH7612, with on-chip 4-kbyte cache and large-capacity 16-kbyte RAM that enable high-speed, real-time processing of large-scale programs, plus a built-in synchronous DRAM interface for high-speed data transfer. Sample shipments will begin in January 1998 in Japan. The SH7612 achieves 87 MIPS system control and 133 MOPS digital signal processing performance at 3.3 V/66 MHz operation.

                      An SH-DSP combines a RISC processor and a DSP, which capable of high-speed processing of voice, image, and other digital signals, on a single chip. Hitachi's initial SH-DSP product, the SH7410, with on-chip 48-kbyte ROM and 8-kbyte RAM, is already in mass production. The SH7410 is widely used to reduce the size and cost of systems, such as digital still cameras, that require both high system control capabilities and advanced digital signal processing performance. The ability to carry out SuperHTM*1-based software development also makes it possible to shorten system development time.

                      The release of the new SH7612, featuring on-chip 4-kbyte cache and large-capacity 16-kbyte RAM, plus a synchronous DRAM interface, will meet the needs of multimedia equipment such as Internet TVs that have to transfer and process large amounts of data, necessitating the use of large-scale programs. Offering high levels of both processing and real-time performance, the SH7612 is a real-time processor suitable for Internet TVs and Internet terminals, TCP-IP-related communication equipment, portable devices such as digital still cameras, and DVD-related products. With a higher operating frequency than the SH7410, plus a compiler version upgrade, the SH7612 achieves performance figures of 87 MIPS and 133 MOPS at 3.3 V/66 MHz operation.

                      To handle high-speed processing of enormous quantities of composite data, including text, voice, and image, in home multimedia equipment such as Internet TVs and digital still cameras, the SH7612 is equipped with 4-kbyte on-chip cache that enables the 87 MIPS CPU performance to be exploited to the full. Its large-capacity 16-kbyte on-chip RAM, meanwhile, allows storage of the large programs and large amounts of data required for JPEG*1, ADPCM*3, and similar DSP processing. The result is one-cycle on-chip memory access at 66 MHz, enabling high-speed processing to be achieved.

                      In addition, the provision of an on-chip synchronous DRAM interface and the use of DMAC enable high data transfer speeds of 100 Mbytes/second or more to be achieved, ensuring full exploitation of the CPU's 87 MIPS processing performance and supporting the transfer of large quantities of image, voice, and other data associated with multimedia applications. The SH7612 also provides various functions required for multimedia equipment on a single chip. These include IrDA 1.0 serial communication interface with FIFO for cableless environments, an IC card interface (smart card interface) for making electronic payments, and the voice CODEC interface (serial I/O interface) used as standard in DSP applications. These built-in functions make it possible to shorten application program and system development times significantly, and to reduce system size and cost.

                      The SH7612 uses a 0.35 micrometer Al 3-layer process, and is housed in a 176-pin LQFP package. In addition to system support provided by development cross-software and the E8000 and E10 emulators, application software (middleware) and a signal processing library are also being developed, and will be released as development is completed. Future plans for expansion of the SH7610 series offering different RAM capacities. A low-priced version with fewer supporting module functions is also planned, to be made available in a 144-pin package. SH-DSP developments will include versions with on-chip high-speed flash memory or on-chip large-capacity flash memory, versions with enhanced timer and interface functions, and ASSP products.

                      Notes:
                      1. SuperHTM: SuperH is a trademark of Hitachi, Ltd.
                      2. JPEG (Joint Photographic (coding) Experts Group): International standard for colors still image compression/decompression.
                      3. ADPCM (Adaptive Differential Pulse Code Modulation): Representative voice data compression/decompression method using differentials.

                      Application Product Examples

                      Consumer Products

                      • Information TVs (high-speed data transfer, voice/image compression/decompression, voice response/recognition, system control)
                      • Digital still cameras (high-speed software JPEG image compression processing, system control)
                      • Multimedia products (voice/image compression/decompression, voice response/recognition, system control)
                      • Digital audio broadcasting (OFDM demodulation, MPEG audio decoding)
                      • Electronic musical instruments (PCM sound source, effector, system control)
                      Communication Equipment
                      • Digital cellular phones (voice compression/decompression, channel codec, protocol control, system control)
                      • PHS (voice compression/decompression, channel codec, protocol control, system control)
                      • Modems (modulation/demodulation, channel codec, protocol control, system control)
                      • LAN adapters (high-speed data transfer)
                      Information and OA Product
                      • Fax (fax image compression, modems, system control)
                      • HDDs (high-speed servo control, system control)
                      • PDAs and similar portable information devices (voice/image compression/decompression, voice response/recognition, communication, system control, data processing)
                      Industrial/Automotive Applications Industrial/Automotive Applications
                      • FA, NC (sequence and servo control)
                      • Car navigation (voice recognition/response functions, addition of high-definition still-image display functions, etc.)
                      • Automotive applications (knocking control, active suspension, noise cancellation)
                      Pricing in Japan

                      Catalog No Unit Price for 10.000 Lot (Yen/ 1 quantity)
                      HD6417612F
                      2,500

                      Features

                      1. SH-DSP: Combination of RISC and DSP
                      A three-bus configuration and one-cycle multiply-and- accumulate operations result in 87 MIPS system control and 133 MOPS high-speed processing performance at 3.3 V/66 MHz operation. This enables system size and cost to be reduced in fields that require both high-level system control capabilities and digital signal processing. For example, use of the SH7612 in a digital still camera enables high-speed JPEG processing to be performed, with the ability to compress a 640 x 480 VGA* screen in less than 0.36 seconds (in the case of a Y: Cr:Cb ratio of 4:1:1). Also, ADPCM voice compression, the principal kind of signal processing in PHS portable terminals, can be executed using approximately 1/6 of the SH-DSP's processing power, enabling the remaining processing power to be used for other functions, such as communication control.

                      Note:
                      * VGA (Video Graphics Array): A graphics display standard used by IBM Corp. in personal computers. This is the mainstream screen format for popular notebook PCs, with 640 x 480 pixels.

                      2. Mixed CPU and DSP instructions, and instructions with full SH-1 and SH-2 upward-compatibility

                      • Highly efficient RISC/DSP program development is possible in a single software environment.
                      • Existing SuperH software resources can be used, and DSP functions can be added easily.
                      • The C compiler offers improved software development efficiency, and signal processing functions can be introduced easily through the use of DSP libraries and middleware.

                      3. Large-capacity on-chip memory
                      The provision of on-chip 4-kbyte cache and 16-kbyte RAM enables on-chip memory access by the CPU/DSP in one clock cycle, and allows operation at a maximum operating frequency of 66 MHz.

                      4. Powerful on-chip external interface functions and peripheral functions.

                      • Direct connection of external memory (SRAM, synchronous DRAM, DRAM, EDO DRAM, burst ROM)
                      • Two-channel DMAC
                      • Three-channel multifunction timer
                      • Single-channel 16-bit timer
                      • Two-channel serial communication interface with FIFO and IrDA
                      • Single-channel serial communication interface with smart card interface
                      • Three-channel synchronous serial interface
                      • 29-bit I/O port
                      Specifications
                      Item Specification
                      Process 0.35 micrometer Al 3-layer
                      Power supply voltage 3.0 to 3.6 V
                      Operating frequency 66 MHz
                      Processing speed CPU: 87MIPS, DSP:133MOPS
                      CPU core 32-bit SH-RISC core version with enhanced DSP functions, "SH-DSP"
                      CPU: Sixteen 32-bit general registers
                      DSP: Six 32-bit data registers
                      Two 40-bit data registers
                      64-bit MAC register
                      CPU instructions 16-bit instructions: 62 kinds (full SH-1, SH-2 upward-compatibility)
                      DSP instructions 16-bit instructions: 8 kinds
                      32-bit instructions: 4 kinds(data transfer) x 21 kinds (data operations) = 84 kinds
                      DSP multiply-and-accumulate functions 16 bits x 16 bits + 40 bits-> 40 bits: 1 cycle
                      16 bits x 16 bits -> 32 bits: 1 cycle
                      32 bits x 32 bits-> 64 bits x 64 bits:2 to 4 cycles
                      32 bits x 32 bits -> 64 bits:2 to 4 cycles
                      DSP functions
                      • Parallel execution of data transfer instructions and data operation instructions (max. 4 instructions in parallel)
                      • DSP instruction support for multiplication, addition, logical operations and barrel shifter
                      • Saturation instructions
                      • Conditional branch instructions
                      • Overhead-less repeat instructions
                      • Modulo addressing
                      Cache 4-kbyte, write-through/write-back methods
                      On-chip RAM 16-kbyte
                      External memory
                      • Supports direct connection to Synchronous DRAM, EDO DRAM, DRAM, burst ROM , and other memory types.
                      • Five 32MB areas
                      • Various wait cycles, and idle cycles for preventing bus collisions, can be set
                      • Data bus width: 8/16/32 bits
                      On-chip supporting functions
                      • DMAC x 2 channels
                      • Serial communication interface with smart card interface (synchronous/ asynchronous) x 2 channels
                      • Serial communication interface with FIFO and IrDA (asynchronous only) x 2 channels
                      • Synchronous serial interface x 3 channels
                      • Multifunction 16-bit timer unit x 3 channels
                      • 16-bit free-running timer
                      • Divider
                      • Interrupt controller
                      • I/O ports x 29
                      • Clock pulse generator: built-in multiplication PLL
                      On-chip debugging functions
                      • Break controller x 2 channels
                      • Hitachi serial debug interface, connectable to JTAG interface
                      • 4-level PC branch address trace FIFO
                      Package LQFP176
                      0.5 mm pitch
                      24 mm x 24 mm


                      WRITTEN BY Secretary's Office
                      All Rights Reserved, Copyright (C) 1997, Hitachi, Ltd.

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