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                      | HITACHI HOME | UP | SEARCH | HITACHI

                      News Release

                      January 26, 1998

                      Hitachi Releases the Industry's First 128M Bit EDO and Synchronous DRAM Products

                      - Achieved using two 64M bit DRAM chips stacked in a standard 400-mil TSOP package -

                      Hitachi, Ltd. today announced the release of four new memory product series for main and expansion memory in PCs and engineering workstations. Two of these series, the HM5113805TD (x 8 bits, 4k refresh) and the HM5113165TD (x16 bits, 4k refresh), are 128M bit EDO DRAMs that use a stacking technology and provide access times of 60 ns, and the other two series, the HM 5212805TD (x 8 bits) and the HM5212165TD (x16 bits), are128M bit synchronous DRAMs that use the same stacking technology and support a PC 66MHz memory bus. The EDO products will be available in sample quantities at the end of January 1998, and the SDRAM products will be available in sample quantities in February 1998.

                      These products each use two Hitachi 64M bit DRAM chips (either EDO or synchronous) molded together in a standard package using Hitachi's stacking technology. The EDO product uses the same package as earlier 64M bit DRAMs, and the SDRAM product uses the same package (a 400-mil 54-pin TSOP II package) will be used for 128M bit SDRAMs and 256M bit SDRAMs.

                      The trends towards further miniaturization and increased memory capacities in PCs are accelerating. For example, while most notebook PCs currently have 32M bytes of main memory, it is expected that 64M bytes will become standard by the middle of 1998. At the same time, there are strong demands for further miniaturization in these products to provide improved portability, and thus it is simply not possible to provide more space for memory chips in such systems. In particular, while four 64M bit DRAMs are now used to provide 32M bytes of onboard memory, it would be difficult to expand this to 64M bytes. Hitachi developed the 128M bit DRAM to allow larger memory capacities to be achieved in such limited spaces.

                      In the EDO products, the HM5113805TD series provides an x 8-bit structure by stacking two x 4-bit 64M byte EDO DRAM chips within the package and molding them together into a single unit. Similarly, the HM5113165TD series provides a x16-bit structure by stacking two x 8-bit 64M byte EDO DRAM chips within the package and molding them together. In the same way, in the SDRAM products, the HM 5212805TD series and HM5212165TD series are formed using two 64M bit synchronous DRAM chips; using two x4-bit chips to form an x8-bit structure and two x8-bit chips to form a x16-bit structure, respectively.

                      Since these stacked products all use the same 400-mil TSOP-II package as 64M bit products, they can easily replace 64M bit products. Thus these products can double memory capacities without increasing the mounting space required. 8k refresh versions of the EDO products are available. It is planned to expand the product line up.

                      Application Product Examples

                      • Onboard memory for notebook personal computers
                      • Main and expansion memory in personal computers and engineering workstations

                      Pricing in Japan

                      • 128M bit DRAM (EDO)
                      Product NameStructureRefresh periodSample price (Yen)
                      HM5113805TD-616M x 84k/64ms7,500
                      HM5113165TD-68M x 164k/64ms7,500
                      HM5112805TD-616M x 88k/64ms7,500
                      HM5112165TD-68M x 168k/64ms7,500

                      • 128M bit SDRAM
                      Product NameStructureRefresh periodSample price (Yen)
                      HM5212805TD-104M x 8 x 4 banks4k/64ms10,000
                      HM5212165TD-102M x 16 x 4 banks 4k/64ms10,000

                      Supplementary Documentation

                      1) EDO DRAM

                      • x8 bit structure
                      HM5113805TD series (4k refresh version) and HM5112805TD series (8k refresh version)

                      HM5113805TD seriesHM5112805TD series
                      Product structure16,777,216-word x 8-bit Dynamic RAM
                      Power-supply voltage3.3-V single-voltage power supply (+/-0.3 V)
                      Access time60ns (max)
                      Power dissipation
                      Operating: 792 mW
                      (maximum)
                      Operating: 720 mW
                      (maximum)
                      Standby: 3.6 mW (maximum)Standby: 3.6 mW (maximum)
                      (CMOS interface)(CMOS interface)
                      High-speed access modeEDO page mode
                      Refresh format
                      4,096cycle/64ms8,192cycle/64ms

                      RAS-only refresh
                      CAS-before-RAS refresh
                      Hidden refresh
                      Package400-mil 32-pin plastic TSOP II (TTP - 32DE)

                      • x 16-bit
                      HM5113165TD series (4k refresh version) and HM5112165TD series (8k refresh version)

                      HM5113165TD seriesHM5112165TD series
                      Product structure8,388,608-word x 16-bit Dynamic RAM
                      Power-supply voltage3.3-V single-voltage power supply (+/-0.3 V)
                      Access time60ns (max)
                      Power dissipation
                      Operating: 828 mW
                      (maximum)
                      Operating: 756 mW
                      (maximum)
                      Standby: 3.6 mW (maximum)Standby: 3.6 mW (maximum)
                      (CMOS interface)(CMOS interface)
                      High-speed access modeEDO page mode
                      Refresh format
                      4,096cycle/64ms8,192cycle/64ms

                      RAS-only refresh
                      CAS-before-RAS refresh
                      Hidden refresh
                      Package400-mil 50-pin plastic TSOP II (TTP - 50DC)

                      2) SDRAM

                      • x8 bit structure
                      HM521805TD series
                      Product structure4,194,304-word x 8-bit x 4-bank Synchronous Dynamic RAM
                      Power-supply voltage3.3-V single-voltage power supply (+/-0.3 V)
                      Operating clock frequencyPC 66MHz bus
                      Type and functionsLVTTL interface
                      Single RAS pulse system
                      The four banks can be operated simultaneously or independently.
                      Supports both burst read/write and burst read/single write operation.
                      Burst length: Can be set to 1, 2, 4, 8 or full page
                      Supports two types of burst sequence (sequential and interleaved)
                      Supports sequential burst and burst stop operations in full page burst mode.
                      The CAS latency can be set to 2 or 3.
                      Refresh format4,096cycle/64ms

                      Auto refresh
                      Self refresh
                      Package400-mil 54-pin plastic TSOP II

                      • x16 bit structure
                      HM5212165TD series
                      Product structure2,097,152-word x 16-bit x 4-bank Synchronous Dynamic RAM
                      Power-supply voltage3.3-V single-voltage power supply (+/-0.3 V)
                      Operating clock frequencyPC 66MHz bus
                      Type and functionsLVTTL interface
                      Single RAS pulse system
                      The four banks can be operated simultaneously or independently.
                      Supports both burst read/write and burst read/single write operation.
                      Burst length: Can be set to 1, 2, 4, 8 or full page
                      Supports two types of burst sequence (sequential and interleaved)
                      Supports sequential burst and burst stop operations in full page burst mode.
                      The CAS latency can be set to 2 or 3.
                      Refresh format4,096cycle/64ms

                      Auto refresh
                      Self refresh
                      Package400-mil 54-pin plastic TSOP II


                      WRITTEN BY Secretary's Office
                      All Rights Reserved, Copyright (C) 1998, Hitachi, Ltd.

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