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                      | HITACHI HOME | UP | SEARCH | HITACHI

                      News Release

                      May 18, 1998

                      Hitachi Releases 64-Mbit Synchronous DRAMs that Support CAS Latency of 2 Clock Cycles in 100-MHz Memory Bus Systems and 64-MB and 128-MB Synchronous DRAM Modules Using Those Chips

                      - A random access time of 36 ns achieved to support high-speed data processing in personal computers and other information-processing equipment -

                      Hitachi, Ltd.(NYSE:HIT) today announced the release of three 64-Mbit synchronous DRAMs (SDRAMs) that can support a CAS latency*1 of 2 clock cycles in 100- MHz memory bus systems. The HM5264165DTT-A60 (with a 16-bit organization), the HM5264805DTT-A60 (with an 8-bit organization), and the HM5264405DTT-A60 (with a 4-bit organization) are designed for use as main memory in personal computers and workstations. Sample shipments will begin in June 1998 in Japan. These SDRAMs have a 36-ns random access time, which represents a 10- ns improvement over Hitachi's earlier 3-clock cycle CAS latency SDRAMs, to support high-speed data transfers.

                      At the same time, Hitachi also announced the release of four memory modules based on these SDRAMs. Sample shipments of the HB52E88EM-A6D (with a 64-bit organization) and the HB52E89EM-A6D (with a 72-bit organization) 64-MB SDRAM modules and the HB52E168EN-A6D (with a 64-bit organization) and the HB52E169EN-A6D (with a 72-bit organization) 128-MB SDRAM modules, will also begin in June 1998 in Japan.

                      There are microprocessors used in PCs with clock speeds of over 350 MHz, and memory bus speed of DRAMs used in these PCs is 100-MHz. Hitachi already mass produces 64- Mbit SDRAMs that support a 3-clock cycle CAS latency in 100-MHz systems and is now releasing SDRAMs that support a 2-clock cycle CAS latency.

                      The HM5264165DTT-A60, the HM5216805DTT-A60, and the HM 5216405DTT-A60 64-Mbit SDRAMs achieve increased speed and reduced current drain by using a 0.25-micrometer CMOS fabrication process and by adopting an internal voltage step-down circuit.

                      These new products achieve the access time of 6 ns from the clock with a CAS latency of 2 clock cycles. This improves the random access time to 36ns compared to the 46 ns of Hitachi earlier 3-clock cycle CAS latency products.

                      Furthermore, the burst current (Icc4) of 110 mA in the earlier 8-bit organization products has been reduced by about 36% to 70 mA in the current 8-bit organization products. This can provide reduced current drains in end products. The HM5264165DTT-A60 has a 1-Mword x 16-bit x 4-bank organization, the HM5264805DTT-A60, has a 2-Mword x 8- bit x 4-bank organization, and the HM5264405DTT-A60 has a 4-Mword x 4-bit x 4-bank organization, and thus conform to JEDEC (Joint Electron Device Engineering Council) standards. These products are provided in a 54-pin 400-mil TSOP-II package.

                      The memory modules also being released use these SDRAMs and 168-pin DIMMs (dual inline memory modules) that support 2-clock cycle CAS latencies in 100-MHz memory bus systems. The products of this release are the HB52E 88 EM-A6D and the HB52E89EM-A6D 64-MB SDRAM modules and the HB52E168EN-A6D and the HB52E169EN-A6D 128-MB SDRAM modules. All of these products conform to the JEDEC standards.

                      The HB52E88EM-A6D has an 8-Mword x 64-bit x 1-bank organization, whereas the HB52E89EM-A6D has an 8-Mword x 72-bit x 1-bank organization to support ECC*2. These modules use eight (HB52E88EM-A6D) or nine (HB52E 89EM-A6D) of the HM5264805DTT-A60 8-bit organization SDRAM chips on the printed circuit board. The HB52E168 EN-A6D has an 8-Mword x 64-bit x 2-bank organization, whereas the HB52E169EN-A6D has an 8-Mword x 72-bit x 2- bank organization to support ECC. These modules use 16 (HB52E168EN) or 18 (HB52E169EN) of the HM 5264805DTT-A608-bit organization SDRAM chips on the printed circuit board.

                      Additionally, the clock interconnect lengths (the distance between the module connections and the individual SDRAM chips) are equalized within the module printed circuit board to minimize clock skew within the module. Also, resistors are inserted in the clock input and data signal lines to suppress signal reflections and allow operation at the high speed of 100 MHz. Note that a 6-layer design was adopted in the printed circuit board used in these modules to allow adequate ground and power planes to be provided. This holds the power supply impedance to a minimum and reduces noise due to high-speed operation.

                      Note *1. CAS latency: Indicates the number of clock cycles from the input of a read command to data output. These products support CAS latencies of 2 and 3 clock cycles.
                      *2. ECC (error checking and correction): Functions that both check for errors that occur in memory data and that correct those errors.

                      Application Product Examples

                      Main memory in personal computers, workstations, and other computer systems

                      Pricing in Japan

                      - 64-Mbit Synchronous DRAM
                      Catalog No. OrganizationSample price (Yen)
                      HM5264165DTT-A601M x 16 bits x 4 banks2,500
                      HM5264805DTT-A602M x 8 bits x 4 banks2,500
                      HM5264405DTT-A604M x 4 bits x 4 banks2,500

                      - Synchronous DRAM Modules
                      Catalog No.OrganizationSample price (Yen)
                      HB52E88EM-A6D8M x 64bit22,000
                      HB52E89EM-A6D8M x 72bit24,500
                      HB52E168EN-A6D16M x 64bit44,000
                      HB52E169EN-A6D16M x 72bit49,000

                      Features

                      1. Support for a CAS latency of 2 clock cycles in 100-MHz memory bus systems This allows the construction of even faster systems. These products support 100-MHz memory bus systems.
                      2. Low power These products can contribute to reductions in the total system power consumption and to longer battery life in portable systems.
                      Specifications

                      1. 64-Mbit Synchronous DRAM
                      ItemHM5264165DTT-A60 HM5264805DTT-A60HM5264405DTT-A60
                      Memory organization 1 Mword x 16 bits x 4 banks2 Mwords x 8 bits x 4 banks4 Mwords x 4 bits x 4 banks
                      External power-supply voltage3.3 V +/- 0.3 V
                      High-speed modesBurst data transfers with burst lengths of 1, 2, 4, 8, or full.
                      Clock frequency100 MHz
                      Access time (tAC)CL=26ns
                      CL=36ns
                      Setup and hold times2ns / 1ns
                      Current drain (Icc4)CL=280mA70mA60mA
                      CL=3100mA85mA80mA
                      FunctionsBurst stop
                      Burst read
                      Single write
                      Auto precharge
                      Clock suspend
                      DQM control
                      Self/auto-refresh
                      Process0.25-micrometer
                      CMOS process
                      Package54-pin 400-mil TSOP-II

                      2. Synchronous DRAM Modules
                      ItemHB52E88EM-A6DHB52E89EM-A6DHB52E168EN-A6DHB52E169EN-A6D
                      Memory organization8 Mwords x 64 bits8 Mwords x 72 bits16 Mwords x 64 bits16 Mwords x 72 bits
                      External power-supply voltage3.3V +/- 0.3V
                      High-speed modesBurst data transfers with burst lengths of 1, 2, 4, 8, or full.
                      Clock frequency100MHz
                      Access time (tAC)CL=26ns
                      CL=36ns
                      Setup and hold times2ns / 1ns
                      FunctionsBurst stop
                      Burst read, single write
                      Auto precharge
                      Clock suspend
                      DQM control
                      Self/auto precharge
                      Package168-pin DIMM (dual inline memory module)
                      133.37 x 34.93 x 4.0 mm


                      WRITTEN BY Secretary's Office
                      All Rights Reserved, Copyright (C) 1998, Hitachi, Ltd.

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