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                      News Release
                      September 28, 1998

                      Hitachi Releases Two 4-Mbit, Low-Power SRAM Series Using Ultra-Small TFBGA Package

                      - Use of a TFBGA package-approximately half the size of previous Hitachi packages-and a x16-bit configuration meet the demand of portable products for small size, high speed, and low power consumption -

                      Hitachi, Ltd.(HYSE: HIT) today announced the release of two series of 4-Mbit low-power SRAMs-the speed-oriented HM62W16256B series (3.3 V models) and the HM62V16256B series (3.0 V models) designed for lower power consumption-that employ an ultra-small TFBGA (thin fine pitch ball grid array) package, a type of CSP (chip scale package). Sample shipments will begin in November 1998 in Japan.

                      The use of a 48-pin TFBGA, approximately half the size of a 44-pin TSOP-II package, together with a x16-bit configuration and reduced current dissipation, offer a solution to the requirements of small size, high speed, and low power consumption in portable phones and portable information devices. With no need for refreshing, low-power SRAM can retain its data at a low voltage. This feature has led to its widespread use in small systems such as portable devices and various kinds of terminals, and in memory cards, computer-related equipment, OA equipment, and so on.

                      Also, with the continuing trend toward lower operating voltages in microprocessors and peripheral LSIs, and the remarkable popularity of battery-driven products such as handheld terminals, notebook PCs and OA devices, and electronic notepads, there are growing calls for low-voltage operation of low-power SRAMs, in addition to the ongoing demand for higher speed.

                      In response to this demand, Hitachi is already mass-producing the HM62W8512A series of 4-Mbit low-power SRAMs, featuring 3.3 V operation and a x8-bit configuration, which meet the need for large capacity, high speed, and low power consumption.

                      Following on from this series, Hitachi has now developed two series of low-power 4-Mbit SRAMs employing a new 48-pin TFBGA package and a x16-bit configuration, specifically to meet the demand for small size, light weight, high speed, and low power consumption in portable phones and other portable devices.

                      With a 256 k x 16-bit configuration and the use of 6 MOS (full CMOS) memory cells, these two new series feature a data retention current of only 1 microA (max.), less than one tenth that of Hitachi products using conventional TFT load type memory cells. In addition, the use of a 0.35 micrometers CMOS process and a circuit design technology, has resulted in a low operating voltage of 2.7 V to 3.6 V (HM62V16256B series) and high speed, with a fastest access time of 55 ns (HM62W16256B series, 3.3 V +/- 0.3V power supply voltage).

                      The newly developed TFBGA package is a type of CSP with a mounting area approximately half that of a 44-pin TSOP-II package. This TFBGA package has been developed to the commercial production stage by adding major improvements in terms of mass-producibility and reliability to the BGA(R)* technology introduced by Tessera, Inc.

                      A 44-pin TSOP-II package will also be available concurrently with a 48-pin TFBGA package. There are two access times for the HM62W16256B series (55 or 70 ns) and for the HM62V16256B series (70 or 85 ns), and two types-L and SL-are available with various differences in current dissipation. Each series includes eight models to meet a wide variety of needs.

                      Future plans include the development of products with even lower operating voltages in the range 2.3 V to 2.7 V. In addition, work is in progress on a TSOP package product with one /CS function pin, offering pin-compatibility with high-speed SRAM, to meet the demand for memory systems with even higher performance.

                      Note*: BGA is a registered trademark of Tessera, Inc.

                      Typical Applications

                      Portable phones
                      Portable information terminals
                      Electronic notepads
                      POS and other handheld terminals
                      Memory cards

                      Features

                      1. Ultra-Small Package
                      An ultra-small TFBGA package, a type of CSP, has been developed, enabling an approximately half the size of a 44-pin TSOP-II package in mounting area.

                      2. 256-kword x 16-Bit Configuration
                      These are Hitachi's first commercial 4-Mbit low-power SRAMs with a 256-kword x 16-bit configuration.

                      3. Low Current Dissipation
                      The data retention current has been reduced to only 1 microA (max.), less than one tenth that of previous Hitachi products, allowing long-term data retention on battery backup.

                      4. High Speed
                      The 3.3 V HM62W16256B Series features a 55 ns access time, enabling low-voltage operation to be achieved without sacrificing system performance.

                      5. Battery Backup
                      Two chip enable pins (CS1 and CS2) provide easy data retention mode control.

                      Prices in Japan
                      Product Code Power Supply Voltage Package Access Time Current Dissipation Sample Price (Yen)
                      HM62W16256BLTT-5 3.3 V +/- 0.3 V TSOP 55ns L version 1,750
                      HM62W16256BLTT-7 70ns 1,700
                      HM62W16256BLTT-5SL 55ns SL version 1,750
                      HM62W16256BLTT-7SL 70ns 1,700
                      HM62W16256BLBT-5 TFBGA 55ns L version 1,750
                      HM62W16256BLBT-7 70ns 1,700
                      HM62W16256BLBT-5SL 55ns SL version 1,750
                      HM62W16256BLBT-7SL 70ns 1,700
                      HM62V16256BLTT-7 2.7 V to 3.6 V TSOP 70ns L version 1,800
                      HM62V16256BLTT-8 85ns 1,750
                      HM62V16256BLTT-7SL 70ns SL version 1,800
                      HM62V16256BLTT-8SL 85ns 1,750
                      HM62V16256BLBT-7 TFBGA 70ns L version 1,800
                      HM62V16256BLBT-8 85ns 1,750
                      HM62V16256BLBT-7SL 70ns SL version 1,800
                      HM62V16256BLBT-8SL 85ns 1,750

                      Specifications
                      Item HM62V16256B HM62W16256B
                      Memory configuration 256 k x 16
                      Power supply voltage (Vcc) 2.7 V to 3.6 V 3.3 V +/- 0.3 V
                      Access time from CS 70/85ns (max.) 55/70ns (max.)
                      Access time from address 70/85ns (max.) 55/70ns (max.)
                      Access time from OE 35/45ns (max.) 35/35ns (max.)
                      Average operating current (minimum cycle) 70/65mA (max.) 80/70mA (max.)
                      TTL standby current 0.3 mA (max.)
                      CMOS standby current L version 0.5microA(typ.) 20 microA(max.)
                      SL version 0.5 microA(typ.) 2 microA(max.)
                      Data retention voltage 2 V (min.)
                      Data retention current L version 0.5 microA(typ.) 10 microA(max.)
                      SL version 0.5 microA(typ.) 1 microA(max.)
                      Input/output level ViH 2.0 V to VCC + 0.3 V 2.0 V to VCC + 0.3 V
                      ViL -0.3 V to 0.6 V  -0.3 V to 0.8 V
                      Packages 48-pin TFBGA (0.75 mm ball pitch)
                      44-pin TSOP type II
                        

                          
                      WRITTEN BY Secretary's Office
                      All Rights Reserved, Copyright (C) 1998, Hitachi, Ltd. 
                       

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