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                      News Release
                      October 12, 1998

                      Hitachi Releases Industry's Highest Speed 64-Mbit Synchronous DRAMs

                      - 133 MHz operation with CAS latency of 2, plus low-voltage operation (2.5 V power supply voltage) - 

                      Hitachi, Ltd. (NYSE:HIT) today announced the release of six 133 MHz memory bus compatible 64-Mbit synchronous DRAM (SDRAM) models, for use as main memory in personal computers and workstations, that feature the highest speed in the industry and a small chip size (38 mm2). Sample shipments will begin in November 1998 in Japan. 

                      The lineup comprises the low-voltage HM52Y64165FTT-75 (x16-bit configuration), HM52Y64805FTT-75 (x8-bit configuration), and HM52Y64405FTT-75 (x4-bit configuration), with a power supply voltage of 2.5 V, and the HM5264165FTT-75 (x16-bit configuration), HM5264805FTT-75 (x8-bit configuration), and HM5264405FTT-75 (x4-bit configuration), with a power supply voltage of 3.3 V. All models increase operating speed from the previous 100 MHz to 133 MHz with a CAS latency* of 2. The 2.5 V power supply voltage models also offer an approximately 40% reduction in power consumption compared with previous products. 

                      SDRAMs supporting a 100 MHz memory bus are currently the mainstream devices for use as main memory in personal computers and workstations, but with future increases in CPU speed, a shift in memory bus speed to 133 MHz can also be expected for high-end machines.
                      Hitachi already mass-produces 64-Mbit SDRAMs supporting a 100 MHz memory bus with a CAS latency of 2, and is now offering models supporting a 133 MHz memory bus. 
                      The new SDRAMs employ an ultrafine 0.18 m process and cutting-edge memory cell technology to achieve a small chip size, for a 64-Mbit SDRAM, of 38 mm2. The smaller chip size together with improved device performance has cut the access time from a read command from 16 ns to 13 ns, resulting in the industry's highest speed 133 MHz operation with a CAS latency of 2. 

                      In addition, special internal power supply circuit features have made it possible to achieve 2.5 V operation and lower power consumption, with operating power consumption cut by approximately 40% from the previous 360 mW (x8-bit configuration model in 100 MHz burst operation) to 200 mW. 

                      The new SDRAMs use the same 54-pin, 400 mil TSOP-II package as previous models. Future plans include the development of 128-Mbit models using a laminated package technology in which two SDRAMs are mounted in a single package, and also modules containing these SDRAMs. 

                      Note*: CAS latency: The number of clocks from read command input to data output. These SDRAMs support CAS latencies of 2 and 3. 

                      Typical Applications
                      Main memory in personal computers and workstations 

                      Prices in Japan
                      Product Code Operating Voltage Configuration Sample Price (Yen)
                      HM52Y64165FTT-75 2.5 V +/- 0.2 V 1Mx16x4 banks 2,500 
                      HM52Y64805FTT-75 2Mx8x4 banks
                      HM52Y64405FTT-75 4Mx4x4 banks
                      HM5264165FTT-75 3.3 V +/- 0.3 V 1Mx16x4banks 2,100 
                      HM5264805FTT-75 2Mx8x4banks
                      HM5264405FTT-75 4Mx4x4 banks

                      Specifications
                      Item HM52Y64165FTT-75
                      HM5264165FTT-75
                      HM52Y64805FTT-75
                      HM5264805FTT-75
                      HM52Y64405FTT-75
                      HM5264405FTT-75
                      Memory configuration 1M wordsx16 bitsx4 banks 2M wordsx8 bitsx4 banks 4M wordsx4 bitsx4 banks
                      External power supply voltage 2.5 V +/- 0.2 V
                      3.3 V +/- 0.3 V
                      High-speed mode Burst data transfer (burst length: 1/2/4/8/full)
                      Clock frequency 133 MHz
                      Access time CL=2 5.5 ns
                      tAC CL=3 5.5 ns
                      Setup/hold 2 ns /1 ns
                      Functions Burst stop, burst read
                      Single write
                      Auto-precharge
                      Clock suspend
                      DQM control
                      Self-/auto-refresh 
                      Process 0.18 m CMOS process
                      Package 54-pin, 400 mil TSOP-II
                        

                         
                      WRITTEN BY Secretary's Office
                      All Rights Reserved, Copyright (C) 1998, Hitachi, Ltd. 
                       

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