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                      | HITACHI HOME | UP | SEARCH | HITACHI

                      News Release ^
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                      September 9, 1999

                      Hitachi Releases Industry's First 512-Mbit Synchronous DRAMs

                      -Stacking technology used to house two memory chips in one package, giving twice the capacity of 256-Mbit SDRAM in the same package -

                      Hitachi, Ltd. (TSE: 6501) today announced the industry's first 512-bit synchronous DRAMs 
                      (SDRAMs)-the HM5251165BTD Series (x16-bit configuration), HM5251805BTD Series 
                      (x8-bit configuration), and HM5251405BTD Series (x4-bit configuration)-for use as main 
                      and expansion memory in personal computers, workstations, servers, and similar products.  
                      Sample shipments will begin in October 1999 in Japan.  These new products employ Hitachi's 
                      proprietary stacking technology to achieve integrated molding of two 256-Mbit SDRAM 
                      chips, enabling the chips to be housed in the same 54-pin, 400-mil* TSOP-II package as a 
                      256-Mbit SDRAM.
                      
                      With the increasing system performance and capacity of information devices such as personal 
                      computers and workstations, the capacity of the installed memory also continues to grow.  
                      Meanwhile, the physical size of systems continue to shrink, restricting the space available for 
                      memory installation.  This has led to the demand for greater capacity per unit SDRAM in 
                      order to achieve high-density mounting.
                      
                      As a means of increasing unit memory capacity, Hitachi developed a stacking technology 
                      whereby two memory chips are placed one above the other within a single package, and 
                      already has 128-Mbit SDRAMs, employing two 64-Mbit SDRAM chips, in production.  
                      Using this same technology, Hitachi has now developed the industry's first 512-Mbit 
                      SDRAMs, employing two stacked 256-Mbit SDRAM chips.
                      
                      These new products have a pin arrangement that is upward-compatible with 256-Mbit 
                      SDRAMs, and provide twice the memory capacity in the same 54-pin, 400-mil TSOP-II 
                      package mounting space.  They also support a 100 MHz memory bus (PC100).
                      
                      Future plans include the development of a model offering 133 MHz memory bus (PC133) 
                      support.
                      
                      Note: * 100 mil = 2.54 mm
                      
                      < Typical Applications >
                      Main and expansion memory in personal computers, workstations, and servers
                      
                      
                      < Prices in Japan > (For Reference Only) 
                      Product Code		Configuration		CAS Latency	Sample Price (Yen)
                      HM5251165BTD-A6		8 Mwords x 16 bits 	CL=2		60,000
                      			x 4 banks                                                 
                      HM5251165BTD-B6		8 Mwords x 16 bits 	CL=3		58,000
                      			x 4 banks                                                 
                      HM5251805BTD-A6		16 Mwords x 8 bits 	CL=2		60,000
                      			x 4 banks                                                 
                      HM5251805BTD-B6		16 Mwords x 8 bits 	CL=3		58,000
                      			x 4 banks                                                 
                      HM5251405BTD-A6		32 Mwords x 4 bits 	CL=2		60,000
                      			x 4 banks                                                 
                      HM5251405BTD-B6		32 Mwords x 4 bits 	CL=3		58,000
                      			x 4 banks                                                 
                      
                      
                      
                      


                      WRITTEN BY Secretary's Office
                      All Rights Reserved, Copyright (C) 1999, Hitachi, Ltd.

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